module sync_module
(
CLK,
RSTn,
VSYNC_Sig,// output - to U3
HSYNC_Sig, // output - to U3
Column_Addr_Sig, // output - to U3
Row_Addr_Sig, // output - to U3
Ready_Sig, // output - to U3
);
	input CLK;
	input RSTn;
	output VSYNC_Sig;
	output HSYNC_Sig;
	output Ready_Sig;
	output [10:0] Column_Addr_Sig;
	output [10:0] Row_addr_Sig;
	reg Vsync_sig;
	reg Hsync_sig;
	reg [10:0] Column_Addr_sig;
	reg [10:0] Row_addr_sig;
	/*************************************************/
	reg [10:0] Count_H; //行像素寄存器
	reg [10:0] Count_V; //列像素寄存器
	
	always@(posedge CLK or negedge RSTn)
	begin
		if(!RSTn)
			   Count_H<=11'd0;
		else if(Count_H==11'd1056)
				Count_H<=11'd0;
		else
				Count_H<=Count_H+1'b1;
	end
	
	always@(posedge CLK or negedge RSTn)
	begin
		if(!RSTn)
			   Count_V<=11'd0;
		else if(Count_V==11'd628)
				Count_V<=11'd0;
		else	if(Count_H ==11'd1056)
				Count_H<=Count_H+1'b1;
	end
	
	
	/***********************************************/
	reg isReady;

 always @ ( posedge CLK or negedge RSTn )
begin
	if( !RSTn )
	isReady <= 1'b0;
	else if( ( Count_H > 11'd216 && Count_H < 11'd1017 ) && ( Count_V > 11'd27 && Count_V < 11'd627 ) )
		isReady <= 1'b1;
	else
		isReady <= 1'b0;
end

 /*********************************/
 //时序

 assign VSYNC_Sig = ( Count_V <= 11'd4 ) ? 1'b0 : 1'b1;
 assign HSYNC_Sig = ( Count_H <= 11'd128 ) ? 1'b0 : 1'b1;
 assign Ready_Sig = isReady; 
 

 /********************************/

 assign Column_Addr_Sig = isReady ? Count_H - 11'd217 : 11'd0; // Count from 0
 assign Row_Addr_Sig = isReady ? Count_V - 11'd28 : 11'd0; // Count from 0

 /********************************/

endmodule
